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| general description the max7306/max7307 i 2 c-/smbus -compatible, seri- al-interfaced peripherals feature four level-translating i/os and operate from a 1.62v to 3.6v power supply. the max7307 features a port supply (v la ) that allows level translation on i/o ports to operate from a separate power supply from 1.4v to 5.5v. the max7306 features an address select input (ad0) to allow up to four unique slave addresses. the max7306/max7307 ports p2, p3, and p4 can be configured as inputs, push-pull outputs, and open-drain outputs. port p1 can be configured as a general-pur- pose input, open-drain output, or an open-drain int out- put. ports p2 and p3 can be configured as oscin and oscout, respectively. the max7306/max7307 include an internal oscillator for pwm, blink, and key debounce, or to cascade multiple max7306/max7307s. the exter- nal clock can be used to set a specific pwm and blink timing. the rst input asynchronously clears the 2-wire interface and terminates a bus lockup involving the max7306/max7307. all ports configured as output feature 33-step pwm, allowing any output to be set from fully off, 1/32 to 31/32 duty cycle, to fully on. all output ports also feature led blink control, allowing blink periods of 1/8 second, 1/4 second, 1/2 second, 1, 2, 4, or 8 seconds. any port can blink during this period with a 1/16 to 15/16 duty cycle. the max7306/max7307 are specified over the -40? to +125? temperature range and are available in 10-pin ?fn (2mm x 2mm) and 10-pin ?ax packages. applications cell phones lcd/keypad backlights system i/o ports led status indicators features ? 1.4v to 5.5v i/o level translation port supply (v la ) ? 1.62v to 3.6v power supply ? four individually configurable gpio ports p1 = open-drain i/o p2, p3, p4 = push-pull or open-drain i/o ? individual 33-step pwm intensity control ? blink controls with 15 steps on outputs ? 1khz pwm period provides flicker-free led intensity control ? 25ma (max) port output sink current (100ma max ground current) ? inputs overvoltage protected up to 5.5v (v la ) ? transition detection with optional interrupt output ? optional input debouncing ? rst input clears serial interface, can restore power-up default state, and synchronizes blink timing ? oscillator input and output enables cascading multiple devices ? low 0.75a (typ) standby current max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers ________________________________________________________________ maxim integrated products 1 ordering information 19-0836; rev 0; 6/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information continued at end of data sheet. pin configurations appear at end of data sheet. evaluation kit available smbus is a trademark of intel corp. ?ax is a registered trademark of maxim integrated products, inc. part top mark pin-package pkg code max7306 alb+ aal 10 ?fn (2mm x 2mm) l1022-1 note: all devices are specified over the -40? to +125? oper- ating temperature range. + denotes lead-free package. c sda gnd +1.8v v dd v la p2/oscin p3/oscout p4 +4.5v max7307 scl rst int sda scl rst p1/int ad0 c sda gnd +2.5v v dd p2/oscin p3/oscout p4 max7306 scl rst int sda scl rst p1/int typical operating circuit
max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (max7306) (v dd = 1.62v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v dd = 3.3v, t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (all voltages referenced to gnd.) v dd ..........................................................................-0.3v to +4v v la , scl, sda, ad0, and rst .................................-0.3v to +6v p1/ int , p2/oscin, p3/oscout, and p4 max7306 ................................................-0.3v to (v dd + 0.3v) max7307.................................................-0.3v to (v la + 0.3v) p1/ int , p2/oscin, p3/oscout, and p4 sink current ......25ma p2/oscin, p3/oscout, and p4 source current ..............10ma sda sink current ...............................................................10ma v dd current .......................................................................10ma v la current (max7307) ......................................................30ma gnd current ....................................................................100ma continuous power dissipation (t a = +70?) 10-pin ?fn (derate 5.0mw/? over +70?) ..............402mw 10-pin ?ax (derate 10.3mw/? over +70?) ............825mw operating temperature range .........................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units operating supply voltage v dd 1.62 3.60 v power-on reset voltage v por v dd rising 1.0 1.3 1.6 v power-on reset hysteresis v porhyst 10 131 300 mv i stb internal oscillator disabled; scl, sda, digital inputs at v dd or gnd; p1?4 (as inputs) at v dd or gnd 0.75 2 standby current (interface idle) i osc internal oscillator enabled; scl, sda, digital inputs at v dd or gnd; p1?4 (as inputs) at v dd or gnd 14 25 ? s up p l y c ur r ent ( inter face runni ng ) i sup f s c l = 400kh z; other d i g i tal i np uts at v dd or gnd 33 40 ? input high voltage sda, scl, ad0 v ih 0.7 x v dd v input low voltage sda, scl, ad0 v il 0.3 x v dd v input high voltage rst , p1?4 v ihp 0.7 x v dd v input low voltage rst , p1?4 v ilp 0.3 x v dd v inp ut leakag e c ur r ent s d a, s c l, ad 0i ih , i il v dd or gnd -1 +1 ? input leakage current rst , p1?4 i ihp , i ilp v dd or gnd -1 +1 ? input capacitance sda, scl, ad0, p1?4 8 pf v dd = 1.62v, i sink = 3ma 0.06 0.11 v dd = 2.5v, i sink = 16ma 0.19 0.4 output low voltage p1?4 v ol v dd = 3.3v, i sink = 20ma 0.2 0.4 v v dd = 1.62v, i source = 0.5ma 1.55 1.6 v dd 2.5v, i source = 5ma v d d - 0.3 2.3 output high voltage p2, p3, and p4 v oh v dd 3.3v, i source = 8ma v d d - 0.4 3.1 v output low voltage sda v olsda i sink = 6ma 0.3 v max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers _______________________________________________________________________________________ 3 electrical characteristics (max7307) (v dd = 1.62v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v dd = 3.3v, v la = 3.3v, t a = +25?.) (note 1) parameter symbol conditions min typ max units operating supply voltage v dd 1.62 3.60 v port logic supply voltage v la 1.40 5.50 v power-on reset voltage v por v dd rising 1.0 1.3 1.6 v power-on reset hysteresis v porhyst 10 131 300 v i stb inter nal osci l l ator d i sab l ed ; s c l, s d a, d i g i tal i np uts at v d d or g n d ; p 1 p 4 ( as i np uts) at v l a or g n d 0.75 2 standby current (interface idle) i osc inter nal osci l l ator enab l ed ; s c l, s d a, d i g i tal i np uts at v d d or g n d ; p 1 p 4 ( as i np uts) at v l a or g n d 14 25 ? s up p l y c ur r ent ( inter face runni ng ) i sup f scl = 400khz; other digital inputs at v la or gnd 33 40 ? port supply current (v la )i vla port (configured as inputs) at v la or gnd 0.05 5 a input high voltage sda, scl, rst v ih 0.7 x v dd v input low voltage sda, scl, rst v il 0.3 x v dd v input is v la referred 0.7 x v la input high voltage p1?4 v ihpa input is v dd referred 0.7 x v dd v input is v la referred 0.3 x v la input low voltage p1?4 v ilpa input is v dd referred 0.3 x v dd v inp ut leakag e c ur r ent s d a, s c l, ad 0, rst i i i i n i i i i i n iss rst , p1?4 8 0.11 pf v dd = 1.62v, i sink = 3ma 0.06 0.11 v dd = 2.5v, i sink = 16ma 0.19 0.4 output low voltage p1?4 v ol v dd = 3.3v, i sink = 20ma 0.2 0.4 v v la = 1.62v, i source = 0.5ma 1.3 1.4 v la = 2.5v, i source = 5ma v la - 0.3 2.3 output high voltage p2, p3, p4 v oh v la = 3.3v, i source = 8ma v la - 0.4 3.1 v output low voltage sda v olsda i sink = 6ma 0.3 v max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers 4 _______________________________________________________________________________________ port, interrupt ( int ), and reset ( rst ) timing characteristics (v dd = 1.62v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v dd = 3.3v, v la = 3.3v (max7307 only), t a = +25?.) (note 1) (see figures 14, 15, and 16) parameter symbol conditions min typ max units f clk = internal oscillator 32 khz oscillator frequency f clk f clk = external input 1 mhz port output data valid high time t ppvh c l 100pf 4 s port output data valid low time (internal or external oscillator running) t ppvl1 c l 100pf (note 2) 1 / f clk ? port output data valid low time (oscillator not running) t ppvl2 c l 100pf 40 ? port input setup time t psu c l = 100pf 0 s port input hold time t ph c l = 100pf 4 s int input data valid time t iv c l = 100pf 4 s int reset delay time from acknowledge t ir c l = 100pf 4 s rst pulse width t w 500 ns rst rising to start condition setup time t rst 900 ns timing characteristics (v dd = 1.62v to 3.6v, t a = t min to t max , unless otherwise noted. typical values are at v dd = 3.3v, v la = 3.3v (max7307 only), t a = +25?.) (note 1) (see figure 8) parameter symbol conditions min typ max units serial-clock frequency f scl 400 khz bus timeout t timeout 31 ms bus fr ee tim e betw een a s top and a s tart c ond i ti on t buf 1.3 ? hold time, (repeated) start condition t hd , sta 0.6 ? repeated start condition setup time t su , sta 0.6 ? stop condition setup time t su , sto 0.6 ? data hold time t hd , dat (note 3) 0.9 ? data setup time t su , dat 100 ns scl clock low period t low 1.3 ? scl clock high period t high 0.7 ? rise time of both sda and scl signals, receiving t r (notes 2, 4) 20 + 0.1c b 300 ns fall time of both sda and scl signals, receiving t f (notes 2, 4) 20 + 0.1c b 300 ns fall time of sda transmitting t f.tx (note 4) 20 + 0.1c b 250 ns pulse width of spike suppressed t sp (note 5) 50 ns c ap aci ti ve load for e ach bus li ne c b (note 2) 400 pf note 1: all parameters are tested at t a = +25?. specifications over temperature are guaranteed by design. note 2: guaranteed by design. note 3: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) to bridge the undefined region of scl? falling edge. note 4: c b = total capacitance of one bus line in pf. t r and t f are measured between 0.3 x v dd and 0.7 x v dd . note 5: input filters on the sda and scl inputs suppress noise spikes less than 50ns. typical operating characteristics (v dd = 3.3v, v la = 3.3v, and t a = +25?, unless otherwise noted.) (max7307) quiescent supply current vs. temperature temperature ( c) quiescent supply current ( a) max7306/7 toc01 -40 -25 -10 5 20 35 50 65 80 95 110 125 0.40 0.45 0.50 0.55 0.60 0.65 0.70 internal oscillator off quiescent supply current vs. temperature temperature ( c) quiescent supply current ( a) max7306/7 toc02 -40 -25 -10 5 20 35 50 65 80 95 110 125 11.0 11.5 12.0 12.5 13.0 13.5 14.0 internal oscillator on active supply current vs. temperature temperature ( c) quiescent supply current ( a) max7306/7 toc03 -40 -25 -10 5 20 35 50 65 80 95 110 125 33.0 33.5 34.0 34.5 35.0 35.5 36.0 f scl = 400khz port open-drain output low voltage vs. sink current sink current (ma) output-voltage low (v) max7306/7 toc04 0 5 10 15 20 25 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 +125 c +25 c -40 c push-pull output high voltage vs. source current source current (ma) output-voltage high (v) max7306/7 toc05 03691215 2.7 2.8 2.9 3.0 3.1 3.2 3.3 -40 c +25 c +125 c internal oscillator vs. temperature temperature ( c) frequency (khz) max7306/7 toc06 -40 -25 -10 5 20 35 50 65 80 95 110 125 31.0 31.5 32.0 32.5 33.0 33.5 34.0 max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers _______________________________________________________________________________________ 5 p1 p2 p3 p4 2.00v/div staggered pwm output max7306/7 toc07 400 s/div c l = 10pf c l = 100pf push-pull output rise time max7306/7 toc08 20ns/div 2v/div max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers 6 _______________________________________________________________________________________ pin description pin max7306 max7307 name function 11 rst reset input. rst is an active-low input, referenced to v dd , that clears the 2-wire interface, which can be configured to put the device in the power-up reset condition and reset the pwm and blink timing. 2 2 p1/ int input/output port. p1/ int is configurable as an open-drain i/o or as a transition detection interrupt output. 3 3 gnd ground 44 p2/oscin input/output port. p2/oscin is configurable as a push-pull i/o, open-drain i/o, or as the pwm/blink/timing oscillator input. 55 p3/oscout input/output port. p3/oscout is configurable as a push-pull i/o, open-drain i/o, or as the pwm/blink/timing oscillator output. 6 6 p4 input/output port. p4 is configurable as a push-pull i/o or an open-drain i/o. ? v la port supply for p1?4. connect v la to a power supply between 1.40v and 5.5v. bypass v la to gnd with a 0.1? capacitor. 7 ad0 address input. sets the device slave address. connect to gnd, v dd , scl, or sda to provide four address combinations. 88v dd positive supply voltage. bypass v dd to gnd with a 0.1? ceramic capacitor. 9 9 sda serial-data i/o 10 10 scl serial-clock input ep ep gnd exposed paddle on ?ax package underside. connect to gnd. max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers _______________________________________________________________________________________ 7 detailed description the max7306/max7307 4-port, general-purpose port expanders operate from a 1.62v to 3.6v power supply. ports p2 through p4 can be configured as inputs, push- pull outputs, and open-drain outputs. port p1 can be configured as an input and an open-drain output; p1 can also be configured to function as an ( int ) output. each port configured as an open-drain or push-pull output can sink up to 25ma. push-pull outputs also have a 10ma source drive capability. the max7306/ max7307 are rated to sink a total of 100ma into any combination of the output ports. output ports have pwm and blink capabilities, as well as logic drive. initial power-up on power-up, the max7307 default configuration has all ports configured as input ports with logic levels ref- erenced to v la . the max7306 default configuration has all ports configured as input ports with logic levels referenced to v dd . the transition detection interrupt status flag resets and stays high (see tables 1 and 2). device configuration registers the device configuration registers set up the interrupt function, serial-interface bus timeout, pwm/blink, oscil- lator options, global blink period, and reset options (see tables 3 and 4). i 2 c output logic i/o p1?4 i/o control register bank max7307 only input logic sda scl max7306 only v la v dd ad0 rst max7306/ max7307 block diagram max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers 8 _______________________________________________________________________________________ register data register power-up condition address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 ports p1?4 ports p_ are v la referred input ports with interrupt and debounce disabled 0x01?x04 1 0 0 0 0 0 0 0 configuration 26 rst d oes not r eset r eg i ster s or counters; b l i nk p er i od i s 1h z; tr ansi ti on fl ag cl ear ; i nterr up t status fl ag cl ear 0x26 1110110 0 configuration 27 ports p1?4 are gpio ports; bus timeout is disabled 0x27 1000111 1 table 2. power-up register status register address autoincrement address por state port p1 or int output 0x01 0x02 0x80 port p2 or oscin input 0x02 0x03 0x80 port p3 or oscout output 0x03 0x04 0x80 port p4 0x04 0x05* 0x80 configuration 26 0x26 0x27 0xec configuration 27 0x27 0x28* 0x8f factory reserved (do not write to these registers) 0x3c?x3f 0x3f?x40 0x00 factory reserved (do not write to these registers) 0x00 0x01 0x80 table 1. register address map * no registers are present. max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers _______________________________________________________________________________________ 9 register bit description value function 0 an interrupt has occurred on at least one interrupt enabled input port. d7 interrupt status flag (read-only) 1* no interrupt has occurred on an interrupt enabled input port. 0 transition has occurred on an input port. d6 transition flag (read-only) 1* no transition has occurred on an input port. d5 reserved 0 reserved. d4, d3, d2 blink prescaler bits 0/1 see table 9 for blink frequency setting. 0* rst does not reset pwm/blink counters. d1 rst timer 1 rst resets pwm/blink counters. 0* rst does not reset registers to power-on-reset state. d0 rst por 1 rst resets registers to power-on-reset state. table 3. configuration register (0x26) * default state. register bit description value function 0 enables the bus timeout feature. d7 bus timeout 1* disables the bus timeout feature. d6, d5, d4 reserved 0 reserved. 0 sets p3 to output the oscillator. d3 p3/oscout 1* sets p3 as a gpio controlled by register 0x03. 0 sets p2 as the oscillator input. d2 p2/oscin 1* sets p2 as a gpio controlled by register 0x02. 0 sets p1 as the interrupt output. d1 p1/ int output 1* sets p1 as a gpio controlled by register 0x01. d0 input transition 0 set to 0 on power-up for proper transition detection. table 4. configuration register (0x27) * default state. max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers 10 ______________________________________________________________________________________ slave address the max7307 is set to slave address 0x98 and the max7306 can be set to one of four i 2 c slave addresses 0x98 to 0x9f, using the address input ad0 (see table 5) and is accessed over an i 2 c or smbus serial interface. the max7306 slave address is determined on each i 2 c transmission, regardless of the transmission actually addressing the device or not. the max7306 distin- guishes whether address input ad0 is connected to sda, scl, v dd , or gnd during the transmission. therefore, the max7306 slave address can be config- ured dynamically in an application without toggling the device supply. i/o port registers the port i/o registers set the i/o ports, one register per port (see tables 6 and 7). use the i/o port registers to configure the ports individually as inputs, open-drain, or push-pull outputs. port p1 can only be configured as an input or an open-drain output. the push-pull bit (d6) set- ting for the port i/o register p1 is ignored. i/o input port configure a port as an input by writing a logic-high to the msb (bit d7) of the port i/o register (see table 6). to obtain the logic level of the port input, read the port i/o register bit, d0. this readback value is the instantaneous logic level at the time of the read request if debounce is disabled for the port (port i/o register bit d2 = 0), or the debounced result if debounce is enabled for the port (port i/o register bit d2 = 1). see figure 1 for input port structure. i/o output port configure a port as an output by writing a logic-low to the msb (bit d7) of the port i/o register. the device reads back the logic level, pwm, or the blink setting of the port (see table 7). device address ad0 c o nn ec tio n a6 a5 a4 a3 a2 a1 a0 r / w gnd 1001100 0/1 v dd 1001101 0/1 scl 1001110 0/1 sda 1001111 0/1 table 5. slave-address selection register bit description value function d7 port i/o set bit 1 sets the i/o port as an input. 0 refers the input to the v la supply voltage. d6* port supply reference 1 refers the input to the v dd supply voltage. 0 disables the transition interrupt. d5 transition interrupt enable 1 enables the transition interrupt. d4, d3 reserved 0 do not write to these registers. 0 disables debouncing of the input port. d2 debounce 1 enables debouncing of the input port. 0 no transition has occurred since the last port read. d1 port transition state (read-only) 1 a transition has occurred since the last port read. 0 port input is logic-low. d0 port status (read-only) 1 port input is logic-high. table 6. port i/o registers (i/o port set as an input, registers 0x01 to 0x04) * bit d6 controls the i/o? supply reference for the max7307. the max7306 ignores bit d6. max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers ______________________________________________________________________________________ 11 debounce logic transition detection transition detection i/o max7307 only 0 1 port_[2] (debounce) interrupt logic int int2 int4 int port_ [5] interrupt enable port_[0] (portin) port_[6] (threshold select) 0 1 v dd v la figure 1. input port structure register bit description value function d7 port i/o set bit 0 sets the i/o port as an output. 0 sets the output type to open-drain. d6 output port set to push-pull or open-drain 1 sets the output type to push-pull. 0 sets the output to pwm mode. d5 pwm/blink enable 1 sets the output to blink mode. 0 msb of the 5-bit duty cycle setting. see the pwm and blink timing section. d4 duty cycle bit 4 1 msb of the 5-bit duty cycle setting. see the pwm and blink timing section. 0 bit 3 of the 5-bit duty cycle setting. see the pwm and blink timing section. d3 duty cycle bit 3 1 bit 3 of the 5-bit duty cycle setting. see the pwm and blink timing section. 0 bit 2 of the 5-bit duty cycle setting. see the pwm and blink timing section. d2 duty cycle bit 2 1 bit 2 of the 5-bit duty cycle setting. see the pwm and blink timing section. 0 bit 1 of the 5-bit duty cycle setting. see the pwm and blink timing section. d1 duty cycle bit 1 1 bit 1 of the 5-bit duty cycle setting. see the pwm and blink timing section. 0 lsb of the 5-bit duty cycle setting. see the pwm and blink timing section. d0 duty cycle bit 0 1 lsb of the 5-bit duty cycle setting. see the pwm and blink timing section. table 7. port i/o registers (i/o port set as an output, registers 0x01 to 0x04) max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers 12 ______________________________________________________________________________________ port supplies and level translation the max7307 features a port supply, v la , that provides the logic supplies to all push-pull i/o ports. p2 through p4 can be configured as push-pull i/o ports (see figure 3). v la powers the logic-high port output voltage sourc- ing the logic-high port load current. v la provides level translation capability for the outputs and operates over a 1.40v to 5.5v voltage independent of the power-supply voltage, v dd . each port of the max7307 set as an input can be config- ured to switch midrail of either the v dd or the v la port supplies. whenever the port supply reference is changed from v dd to v la , or vice versa, read the port register to clear any transition flag on the port. ports p2 through p4 are overvoltage protected to v la . this is true even for a port used as an input with a v dd port logic-input threshold. port p1 is overvoltage pro- tected to 5.5v, independent of v dd and v la (see figure 3). to mix logic outputs with more than one voltage swing on a group of ports using the same port supply, set the port supply voltage (v la ) to be the highest out- put voltage. use push-pull outputs and port p1 for the highest voltage ports, and use open-drain outputs with external pullup resistors for the lower voltage ports. for the max7307, when p2, p3, and p4 ports are acting as an input referenced to v dd, make sure the v la voltage is greater than v dd - 0.3v. select v dd v la input port p1 output p1 p2, p3, p4 select v dd v la input ports p2 through p4 max7307 only max7307 only output figure 3. port i/o structure i/o port_[5] 0 1 clock 5-bit pwm 4-bit blink 3-bit prescaler port_[3:0] port_[4:0] config26 [4:2] figure 2. output port structure max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers ______________________________________________________________________________________ 13 input debounce the max7306/max7307 sample the input ports every 31ms if input debouncing is enabled for an input port (d2 = 1 of the port i/o register). the max7306/max7307 compare each new sample with the previous sample. if the new sample and the previous sample have the same value, the corresponding internal register updates. when the port input is read through the serial interface, the max7306/max7307 do not return the instantaneous backing value of the logic level from the port because debounce is active. instead, the max7306/max7307 return the stored debounced input signal. when debouncing is enabled for a port input, transition detection applies to the stored debounced input signal value, rather than to the instantaneous value at the input. this process allows for useful transition detection of noisy signals, such as keyswitch inputs, without causing spurious interrupts. port input transition detection and interrupt any transition on ports configured as inputs automatically set the d1 bit of that port? i/o registers high. any input can be selected to assert an interrupt output indicating a transi- tion has occurred at the input port(s). the max7306/ max7307 sample the port input (internally latched into a snapshot register) during a read access to its port p_ i/o register. the max7306/max7307 continuously compare the snapshot with the port? input condition. if the device detects a change for any port input, an internal transition flag sets for that port. read register 0x26 to clear the inter- rupt, then read all the port i/o registers (0x01 to 0x04) by initiating a burst read to clear the max7306/max7307 s internal transition flag. note that when debouncing is enabled for a port input, transition detection applies to the stored debounced input signal value, rather than to the instantaneous value at the input. transition bits d4 and d3 of port registers must be set to 0 to detect the next rising or falling edge on the input port (p_). the max7306/max7307 allow the user to select the input port(s) that cause an interrupt on the int output. set int for each port by using the int enable bit (bit d5) in each port p_ register. the appropriate port? transition flag always sets when an input changes, regardless of the port? int enable bit settings. the int enable bits allow processor interrupt only on critical events, while the inputs and the transition flags can be polled periodically to detect less critical events. when debounce is disabled, a signal transition between the 9th and 11th falling edges of the clock will not be regis- tered, since the transition is detected and cleared at the same time. ports configured as outputs do not feature transition detection, and therefore, cannot cause an interrupt. the int output never reasserts during a read sequence because this process could cause a recursive reentry into the interrupt service routine. instead, if a data change occurs during the read that would normally set the int output, the interrupt assertion is delayed until the stop condition. if the changed input data is read before the stop condition, a new interrupt is not required and not asserted. the int bit and int output (if selected) have the same value at all times. transition flag the transition bit in device configuration register 0x26 is a nor of all the port i/o registers?individual transition bits. a port? i/o register? transition bit sets when that port is set as an input, and the input changes from the port? i/o registers last read through the serial interface. a port? individual transition bit clears by reading that port? i/o register. always write a 0 to bits d4 and d3 of the configuration register 0x26 to properly configure a transition detection. the transition flag of configuration register 0x26 is only cleared after reading all ports i/o registers on which a transition has ocurred. rst input the active-low rst input operates as a hardware reset that voids any ongoing i 2 c transition involving the max7306/max7307 (this feature allows the max7306/max7307 supply current to be minimized in power-critical applications by effectively disconnecting the max7307 from the bus). rst also operates as a chip enable, allowing multiple devices to use the same i 2 c slave address if only one max7306/max7307 has its rst input high at any time. rst can be configured to restore all port registers to the power-up settings by setting bit d0 of device configuration register 0x26 ( table 1). rst can also be configured to reset the inter- nal timing counters used for pwm and blink by setting bit d1 of device configuration register 0x26. when rst is low, the max7306/max7307 are forced into the i 2 c stop condition. the reset action does not clear the interrupt output int . the rst input is referenced to v dd and is overvoltage tolerant up to the supply voltage, v la . int output port p1 can be configured as a latching interrupt out- put, int , that flags any transients on any combination of selected ports configured as inputs. any transitions occurring at the selected inputs assert int low to alert max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers 14 ______________________________________________________________________________________ the host processor of data changes at the selected inputs. reset int by reading any port? i/o registers (0x01 to 0x04). standby mode upon power-up, the max7306/max7307 enter standby mode when the serial interface is idle. if any of the pwm intensity control, blink, or debounce features are used, the operating current rises because the internal pwm oscillator is running and toggling counters. when using oscin to override the internal oscillator, the operating current varies according to the frequency at oscin. when the serial interface is active, the operating current also increases because the max7306/max7307, like all i 2 c slaves, have to monitor every transmission. the bus timeout circuit and debounce circuit use the internal oscil- lator even if oscin is selected. internal oscillator and oscin/oscout external clock options the max7306/max7307 contain an internal oscillator nominally at 32khz. the max7306/max7307 always use the internal oscillator for bus timeout and for debounce timing (when enabled). the internal oscillator is also used by default to generate pwm and blink timing. the internal oscillator only runs when the clock output oscout is needed to keep the operating current as low as possible. the max7306/max7307 can use an external clock source instead of the internal oscillator for the pwm and blink timing. the external clock can range from dc to 1mhz and it connects to the p2/oscin port. the p3/oscout port provides a buffered and level-shifted output of the internal oscillator or external clock to drive other devices. select the p2/oscin and p3/oscout port options using the device configuration register 0x27 bits d2 and d3 (see table 2). the p2/oscin port is overvoltage protected to supply voltage v la for the max7307, so the external clock can exceed v dd if v la is greater than v dd . the external clock cannot exceed v dd for the max7306. the port p2 register (see tables 2 and 6) sets the p2/oscin logic threshold (30%/70%) to either the v dd supply or the v la . use oscout or an external clock source to cascade up to four max7306s per master for applications requir- ing additional ports. to synchronize the blink action across multiple max7306s (see figures 4 and 5), use oscout from one max7306 to drive oscin of the other max7306s. this process ensures the same blink frequency of all the devices, but also make sure to syn- chronize the blink phase. the blink timing of multiple max7306s is synchronous at the instant of power-up because the blink and pwm counters clear by each device? internal reset circuit, and by default the device? internal oscillators are off upon power-up. ensure that the blink phase of all the devices remains synchronized by programming the oscin and oscout functionality before programming any feature that causes a max7306? internal oscillator to operate (blink, pwm, bus timeout, or key debounce). configure the rst input to reset the internal timing counters used for pwm and blink by setting bit d1 of device configu- ration register 0x26 (see table 3). p2/oscin p2/oscin p3/oscout p2/oscin p3/oscout p2/oscin p3/oscout max7306/max7307 max7306/max7307 max7306/max7307 max7306/max7307 max7306/max7307 max7306/max7307 figure 4. synchronizing multiple max7306/max7307s (internal oscillator) max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers ______________________________________________________________________________________ 15 pwm and blink timing the max7306/max7307 divide the 32khz nominal internal oscillator osc or external clock source oscin frequency by 32 to provide a nominal 1khz pwm fre- quency. use the reset function to synchronize multiple max7306s that are operating from the same oscin, or to synchronize a single max7306/max7307? blink tim- ing to an external event. configure the rst input to reset the internal timing counters used by pwm and blink by setting bit d1 of the device configuration regis- ter 0x26 (see table 3). the max7306/max7307 use the internal oscillator by default. configure port p2 using device configuration register 0x27 bit d2 (see table 4) as an external clock source input, oscin, if the application requires a par- ticular or more accurate timing for the pwm or blink functions. oscin only applies to pwm and blink; the max7306/max7307 always use the internal oscillator for debouncing and bus timeout. oscin can range up to 1mhz. use device configuration register 0x27 bit d3 (see table 2) to configure port p3 as oscout to out- put a max7306/max7307 s clock. the max7306/ max7307 buffer the clock output of either the internal oscillator osc or the external clock source oscin, according to port d2? setup. synchronize multiple max7306s without using an external clock source input by configuring one max7306 to generate oscout from its internal clock, and use this signal to drive the remaining max7306s?oscin. a pwm period contains 32 cycles of the nominal 1khz pwm clock (see figure 6). set ports individually to a pwm duty cycle between 0/32 and 31/32. for static logic-level low output, set the ports to 0/32 pwm, and for static logic-level high output, set the port register to 0111xxxx (see table 8). the max7306/max7307 stag- ger the pwm timing of the 4-port outputs, in single or dual ports, by 1/8 of the pwm period. these phase shifts dis- tribute the port-output switching points across the pwm period (see figure 7). this staggering reduces the di/dt output-switching transient on the supply and also reduces the peak/mean current requirement. all ports feature led blink control. a global blink period of 1/8 second, 1/4 second, 1/2 second, 1, 2, 4, or 8 seconds applies to all ports. see table 9. any port can blink during this period with a 1/16 to 15/16 duty cycle, adjustable in 1/16 increments. see table 10. for pwm fan control, the max7306/max7307 can set the blink frequency to 32hz. p2/oscin external oscillator external oscillator 0mhz to 1mhz p2/oscin p2/oscin p2/oscin p3/oscout 0mhz to 1mhz p2/oscin p3/oscout p2/oscin max7306 max7306 max7306 max7306 max7306 max7306 figure 5. synchronizing multiple max7306s (external clock) max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers 16 ______________________________________________________________________________________ 01 977 s nominal pwm period output p1 234 output p1 output p1 output p2 output p2 output p2 output p3 output p3 output p4 output p4 next pwm period next pwm period figure 7. staggered pwm phasing between port outputs high impedance low high impedance low high impedance low output low 31/32 duty pwm high impedance low high impedance low high impedance low output low 30/32 duty pwm output static low (static logic-low output or led drive on) output low 2/32 duty pwm 0b0x000000 output static high (static logic-high output or led drive off) high impedance low output low 3/32 duty pwm high impedance low output low 29/32 duty pwm port register value 977 s nominal pwm period (1024hz period) 0b0x000010 0b0x000011 0b0x011101 0b0x011110 0b0x011111 0b0111xxxx 0b0x000001 output low 1/32 duty pwm figure 6. static and pwm port output waveforms max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers ______________________________________________________________________________________ 17 register data pwm setting d7 d6 d5 d4 d3 d2 d1 d0 port p_ is a static logic-level low output port 0 x 0 0 0 0 0 0 port p_ is a pwm output port; pwm duty cycle is 1/32 0 x 0 0 0 0 0 1 port p_ is a pwm output port; pwm duty cycle is 3/32 0 x 0 0 0 0 1 1 port p_ is a pwm output port; pwm duty cycle is 7/32 0 x 0 0 0 1 1 1 port p_ is a pwm output port; pwm duty cycle is 15/32 0 x 0 0 1 1 1 1 port p_ is a pwm output port; pwm duty cycle is 31/32 0 x 0 1 1 1 1 1 port p_ is a static logic-level high output port 0 1 1 1 x x x x table 8. pwm settings on output ports device configuration register 0x66 blink or pwm setting bit d4 blink2 bit d3 blink1 bit d2 blink0 blink or pwm frequency (32khz internal oscillator) (hz) blink or pwm frequency (0hz to 1mhz external oscillator) bl i nk p er i od i s 8 second s ( 0.125h z) 0 0 0 0.125 oscin / 262,144 blink period is 4 seconds (0.25hz) 0 0 1 0.25 oscin / 131,072 blink period is 2 seconds (0.5hz) 0 1 0 0.5 oscin / 65,536 blink period is 1 second (1hz) 0 1 1 1 oscin / 32,768 blink period is a 1/2 second (2hz) 1 0 0 2 oscin / 16,384 blink period is a 1/4 second (4hz) 1 0 1 4 oscin / 8192 bl i nk p er i od i s an 1/8 second ( 8h z) 1 1 0 8 oscin / 4096 bl i nk p er i od i s a 1/32 second ( 32h z) 1 1 1 32 oscin / 1024 pwm x x x 1024 oscin / 32 table 9. blink and pwm frequencies register data blink settings d7 d6 d5 d4 d3 d2 d1 d0 port p_ is a static logic-level low output port 0 x 1 0 0 0 0 0 port p_ is a blinking output port; blink duty cycle is 1/16 0 x 1 0 0 0 0 1 port p_ is a blinking output port; blink duty cycle is 3/16 0 x 1 0 0 0 1 1 port p_ is a blinking output port; blink duty cycle is 7/16 0 x 1 0 0 1 1 1 port p_ is a blinking output port; blink duty cycle is 15/16 0 x 1 0 1 1 1 1 port p_ is a static logic-level high output port 0 1 1 1 x x x x table 10. blink settings on output ports x = don? care. max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers 18 ______________________________________________________________________________________ serial interface serial addressing the max7306/max7307 operate as a slave that sends and receives data through an i 2 c-compatible, 2-wire interface. the interface uses a serial-data line (sda) and a serial-clock line (scl) to achieve bidirectional communication between master(s) and slave(s). a master (typically a microcontroller) initiates all data transfers to and from the max7306/max7307 and gen- erates the scl clock that synchronizes the data trans- fer (see figure 8). the max7306/max7307 sda line operates as both an input and an open-drain output. a 4.7k (typ) pullup resistor is required on sda. the max7306/max7307 scl line operates only as an input. a 4.7k (typ) pullup resistor is required on scl if there are multiple masters on the 2-wire interface, or if the master in a single-mas- ter system has an open-drain scl output. each transmission consists of a start condition (see figure 9) sent by a master, followed by the max7306/ max7307 7-bit slave address plus r/ w bit, a register address byte, one or more data bytes, and finally a stop condition (see figure 9). start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmis- sion with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission (see figure 9). bit transfer one data bit is transferred during each clock pulse. the data on sda must remain stable while scl is high (see figure 10). acknowledge the acknowledge bit is a clocked 9th bit that the recipient uses to acknowledge receipt of each byte of data (see figure 11). thus, each effectively transferred byte requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse, so the sda line is stable low during the high period of the clock pulse. when the master is transmitting to the max7306/max7307, the devices generate the acknowledge bit because the max7306/max7307 are the scl sda t r t f t buf start condition stop condition repeated start condition start condition t su,sto t hd,sta t su,sta t hd,dat t su,dat t low t high t hd,sta reset t wl(rst) figure 8. 2-wire serial interface timing details sda scl start condition stop condition sp figure 9. start and stop conditions sda scl data line stable; data valid change of data allowed figure 10. bit transfer max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers ______________________________________________________________________________________ 19 recipients. when the max7306/max7307 transmit to the master, the master generates the acknowledge bit because the master is the recipient. slave address the max7306/max7307 have a 7-bit long slave address ( figure 12). the 8th bit following the 7-bit slave address is the r/ w bit. set the r/ w bit low for a write command and high for a read command. the first 5 bits of the max7306 slave address (a6?2) are always 1, 0, 0, 1, and 1. slave address bits a1 and a0 are selected by the address input ad0. ad0 can be connected to gnd, v dd , sda, or scl. the max7306 has four possible slave addresses (see table 5), and therefore, a maximum of four max7306 devices can be controlled independently from the same interface. the max7307 features a permanent slave address of 0x98. message format for writing to the max7306/max7307 a write to the max7306/max7307 comprises the trans- mission of the max7306/max7307? slave address with the r/ w bit set to zero, followed by at least 1 byte of information. the first byte of information is the command byte. the command byte determines which register of the max7306/max7307 is to be written to by the next byte, if received (see table 1). if a stop condition is detected after the command byte is received, the max7306/max7307 take no further action beyond stor- ing the command byte (see figure 13). any bytes received after the command byte are data bytes. the first data byte goes into the internal register of the max7306/max7307 selected by the command byte (see figure 14). if multiple data bytes are transmitted before a stop condition is detected, these bytes are generally stored in subsequent max7306/max7307 internal registers because the command byte address autoincrements (see table 1). message format for reading the max7306/max7307 are read using the max7306/ max7307? internally stored command byte as an address pointer the same way the stored command byte is used as an address pointer for a write. the pointer autoincrements after each data byte is read using the scl sda by transmitter clock pulse for acknowledge start condition sda by receiver 12 89 s figure 11. acknowledge sda scl 0 r/w msb lsb ack 1 1 0a0 11 figure 12. slave address saa p 0 slave address register address acknowledge from max7306 d15 d14 d13 d12 d11 d10 d9 d8 acknowledge from max7306 r/w figure 13. register address received max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers 20 ______________________________________________________________________________________ same rules as for a write. thus, a read is initiated by first configuring the max7306/max7307? command byte by performing a write ( figure 13). the master can now read n consecutive bytes from the max7306/ max7307 with the first data byte being read from the register addressed by the initialized command byte (figure 15). when performing read-after-write verifica- tion, remember to reset the command byte? address because the stored command byte address has been autoincremented after the write (see table 1). operation with multiple masters if the max7306/max7307 are operated on a 2-wire interface with multiple masters, a master reading the max7306/max7307 should use a repeated start between the write that sets the max7306/max7307? address pointer, and the read(s) that takes the data from the location(s). this is because it is possible for master 2 to take over the bus after master 1 has set up the max7306/max7307? address pointer, but before master 1 has read the data. if master 2 subsequently changes the max7306/max7307? address pointer, then master 1? delayed read can be from an unexpect- ed location. bus timeout clear device configuration register 0x27 bit d7 to enable the bus timeout function (see table 2), or set it to disable the bus timeout function. enabling the time- out feature resets the max7306/max7307 serial-bus interface when scl stops either high or low during a read or write. if either scl or sda is low for more than 1 2 3 4 5 6 7 8 9 s 1 0 0 1 1 a1 a0 0 a 0 0 0 0 0 1 0 0 a a p t ppv slave address register address msb data lsb scl sda p4?1 start condition r/w data valid a acknowledge from slave acknowledge from slave acknowledge stop write to output ports registers (p4) figure 14. write to output port registers 1 2 3 4 5 6 7 8 9 s 1 0 0 1 1 a1 a0 1 a a scl sda p4?1 data1 t ph t psu data2 data3 data4 na p no acknowledge start condition stop read from input ports registers r/w acknowledge from slave msb data1 lsb msb data4 lsb acknowledge from master figure 15. read from input port registers 1 2 3 4 5 6 7 8 9 s 1 0 0 1 1 1 a0 1 a a msb data2 lsb scl sda p4?1 data1 t iv t iv t ir data2 na p start condition stop data3 int ir t interrupt valid/reset r/w acknowledge from slave acknowledge from master msb data3 lsb no acknowledge figure 16. interrupt and reset timing max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers ______________________________________________________________________________________ 21 nominally 31ms after the start of a valid serial transfer, the interface resets itself and sets up sda as an input. the max7306/max7307 then waits for another start condition. applications information hot insertion serial interfaces sda, scl (and ad0 for the max7306) remain high impedance with up to 5.5v asserted on them when the max7306/max7307 are powered down (v dd = 0v), independent of the voltages on the port supply v la . when v dd = 0v, or if v dd falls below the max7306/max7307? reset threshold, all i/o ports become high impedance. ports p2 through p4 remain high impedance to signals between 0v and the port supply v la for the max7307 and v dd for the max7306. port p1 goes high impedance to signals up to 5.5v. if a signal outside this range is applied to a port, the port? protection diodes clamp the input signal to v la or 0v, as appropriate. if the max7307? v la is lower than the input signal, the port pulls up v la , and the protection diode effectively powers any load on v la from the input signal. this behavior is safe if the current through each protection diode is limited to 10ma. if it is important that i/o ports remain high impedance when all the supplies are powered down, including the port supply v la , then ensure that there is no direct or parasitic path for the max7306/max7307 input signals to drive current into either the regulator providing v la or other circuits powered from v la . one simple way to achieve this is with a series small-signal schottky diode, such as the bat54, between the port supply and the v la input. i/o level translation the open-drain output configuration of the ports allows them to level translate the outputs to lower (but not higher) voltages than the v la supply. an external pullup resistor converts the high-impedance, logic-high condition to a positive voltage level. connect the resis- tor to any voltage up to v la . for interfacing cmos inputs, a pullup resistor value of 220k is a good start- ing point. use a lower resistance to improve noise immunity, in applications where power consumption is less critical, or where a faster rise time is needed for a given capacitive load. driving led loads when driving leds, use a resistor in series with the led to limit the led current to no more than 25ma. choose the resistor value according to the following formula: r led = (v supply - v led - v ol ) / i led where: r led is the resistance of the resistor in series with the led ( ) v supply is the supply voltage used to drive the led (v) v led is the forward voltage of the led (v) v ol is the output low voltage of the max7306/ max7307 when sinking i led (v) i led is the desired operating current of the led (a). for example, to operate a 2.2v red led at 20ma from a 5v supply, r led = (5 - 2.2 - 0.8) / 0.020 = 100 . driving load currents higher than 25ma the max7306/max7307 can sink current from loads drawing more than 25ma by sharing the load across multiple ports configured as open-drain outputs. use at least one output per 25ma of load current; for example, drive a 90ma white led with four ports. the register structure of the max7306/max7307 allows only one port to be manipulated at a time. do not con- nect ports directly in parallel because multiple ports cannot be switched high or low at the same time, which is necessary to share a load safely. multiple ports can drive high-current leds because each port can use its own external current-limiting resistor to set that port? current through the led. power-supply considerations the max7306/max7307 operate with a v dd power-sup- ply voltage of 1.62v to 3.6v. bypass v dd to gnd with a 0.1? capacitor as close as possible to the device. the port supply v la is connected to a supply voltage between 1.40v and 5.5v and bypassed with a 0.1? capacitor as close as possible to the device. the v dd supply and port supply are independent and can be connected to different voltages or the same supply as required. power supplies v dd and v la can be sequenced in either order or together. for the max7307, when a push-pull port is acting as an input referenced to v cc , make sure the vla voltage is greater than v cc - 0.3v. max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers 22 ______________________________________________________________________________________ 123 10 9 8 45 76 scl v dd p4 sda rst p3/oscout gnd p1/int max7306/ max7307 dfn top view v la /ad0* p2/oscin + pin configurations chip information process: bicmos 1 2 3 4 5 10 9 8 7 6 scl sda v dd v la (ad0)* p2/oscin gnd p1/int rst max7306/ max7307 max + p4 p3/oscout ep = exposed paddle ep *ad0 for max7306 v la for max7307 ordering information (continued) ? ) part top mark pin-package pkg code max7306aub+ aaao 10 ?ax-ep* u10e-3 max7307 alb+ aak 10 ?fn (2mm x 2mm) l1022-1 max7307aub+ aaan 10 ?ax-ep* u10e-3 note: all devices are specified over the -40? to +125? oper- ating temperature range. + denotes lead-free package. * ep = exposed paddle. max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers ______________________________________________________________________________________ 23 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 6, 8, 10l udfn.eps ! " # $ "$ %$ & '$ % (( ) max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers 24 ______________________________________________________________________________________ package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) *+ ! ! , , - " " " + -. . + % % .- + % ' " ' ' - ' ) " # $ "$ %$ & '$ % (( - max7306/max7307 smbus/i 2 c interfaced 4-port, level-translating gpios and led drivers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 25 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 10l umax, exppads.eps |
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